D-A converter using R4R ladder? (R2R x2)

Ivan wrote:Hi Harry,
you had bad luck with your new rig   I believe you will get it back soon and in perfect condition.
VBR from Ivan

Hi Ivan,
Yes, it is simply bad luck. But if one buys second-hand then you can expect this sort of think.

People usually have a reason for getting rid of a perfectly good rig. I got rid of the other FT-101ZD because I needed something more portable, fit in a suitcase and give at least 50-Watts out.

The previous owner of the FT-840 probably had an intermittent fault, so instead of investigating, it was easier to trade it in. If it was, say, an overheating or component breakdown on a card, then it could cost something to repair. Dry joints are not always the easiest to find, but that and intermittent connectors are a lot more easy to find. RadioWorld, however put stickers on the radio so that any investigation would invalidate the guarantee.

But I have faith in https://radioworld.co.uk.

In February, I may be here with 50-Watts and a wife who is not so sick. I could be QRV again as EA/...  

BR Harry - SM0VPO

Silly question: If an amateur radio operator's bystander is holding the vertical HF antenna, he is therefore a capacitive route to ground. Could you tune the antenna by giving the bystander a beer, therefore changing the operators electrolytes?

Hi Harry,
you had bad luck with your new rig   I believe you will get it back soon and in perfect condition.

VBR from Ivan

Hi Ivan,
When I thought of the idea I considered several possibilities, but to be a little more clear, my R4R ladder would look something like this:



As you said, a 4-phase clock would double again the bit-rate without increasing the division rate. This I also considered.

But one dissadvantage I can think of is that with a Sawtooth waveform there would be a sudden step from 255 to 0. That step would occur in two 1/2-clock cycles, but this technique would be perfect for increasing the resolution of any waveform without a sudden change. Waveforms such as sine, trianguar, trapezoidal, etc.

I got to thinking about this because of my analogue oscilloscope project. The timebase is not very linear and you can see this clearly. So I was thinking about a wider range generator that was more clean, but I still want a fast timebase to measure RF up to at least 1MHz.

Another disadvantage would be that both counters would need to have a periodic reset to keep them in sync. I could always use 00H data from the first counter as a trigger to reset the second, that way they would receive a sync with every cycle, and solve the rapid waveform problem at the same time.

I also thought about digital so that I could use a PIC processor. The most important part of an oscilloscope is the trigger, so I though that inhibiting the trigger during a sweep, then holding off the sweep until the input waveform has a zero-crossing (or crosses a preset level). That would be really easy with an 8-pin PIC processor.

But I hope that Maj-Lis's health gets better so I can have more time for the hobby.


FYI
I traded in one of my old FT-101ZD's for an FT-840. I figured that the 14kg weight saving would make it more portable and have a better radio for use in Spain. But just my luck, the radio has an intermittent fault, but it has a warranty seal on it. So I had to send it back 3 days before I came here. I could certainly fix it myself, but if it needed a custom board then it could cost a lot. So this means I am rig-less onthis journey.

I have an X1M 5-watt radio, also a HB phasing-method radio, but to stand any chance of a contact with 5-W I have to go up into the mountains and I don't want to leave Maj-Lis for any length of time.

But thanks for your comments on the idea. I feel it iswell worth developing further. But the PCB could be a bit tricky routing 8 + 8 + 8 + 8  
perhaps I could use a motherboard with plug-in counter daughterboards?

Best regards from Harry - EA/SM0VPO (not QRV on HF, just VHF)

Hi Harry,
what an amazing idea! IMHO nobody has tried it, because nobody had imagined it. I think about the idea from left to right and back and it seems to be correct!
What about pushing the idea even further. I imagine using four clock signals shifted for 0, 90, 180 and 240 degrees, feeding four counters and a R8R ladder. That should increase the precision for one more extra bit. Such clock generators should be available on one chip.

Very best regards from
Ivan OK1SIP

Hi again,

I am thinking a LOT more simple. Absolutely really back to basics:

Here I just use nothing more than the VCO to drive a counter. Then I use 8-bits of binary (only 7 shown) to give me a sawtooth waveform.
But this will be limited to about 25MHz from the VCO, divided by 256 = 100kHz sawtooth.

My suggection is that all the 20K resistors from the 4040 are all changed to 40K, BUT a second 40K resistor feeds each junction from a second 4040 that is counting the same clock. In that way the circuit will behave exactly as before.

Now, if I were to invert the clock feeding the second 4040, being an edge-triggered counter, it willl be triggered on the other edge of the clock (because it is inverted).

This means the second counter will be 1/2 a clock-cycle out-of-sync. It will always be 1/2 a clock cycle behind. This will in effect give me a 512 steps from a 256 counter.

So, pushing the CMOS frequency limit to 25MHz, I can get my 100kHz with 9-bit resolution (512 steps with a /256 counter [pair]). In effect, a dual-(almost)-parallel counter will double my bit-rate, without doubling the divide rate. perhapsI am chasing perpetual motion?

Hope you understand?

Perhaps I am chasing perpetual motion? If it were possible then someone would have done it before without using really high-speed counters?

At the moment I am in Spain, with no PCB facilities, nada, silch, nothing. But I have the opportunity to plan for my return home, and I now have Proteus to design PCBs  

BR Harry

hi, i built this generator about a few years ago https://scienceprog.com/avr-dds-signal-generator-v20/
I think back then it was his first version but i see that he only modified the menu.,the circuit is the same. 
My version goes only to 65 khz but it also has a 1,2.,4 mhz output from the cip. 
The cip does not have a lot of eprom memory but the guy takes use of the fact that the signal is periodic so he only maps a half of the wave. Then the signal is reconstructed only by the way he reads the memory.
I did not really understood how he generates noise, when watched with a scope it really looks like noise, not some repeating pattern.

http://85.226.178.87/eprom/epromosc.htm

Hi you guys,
The medical urgencies have subsided and I can spend more time here, at least for the forseeable future. But my mind has been working a bit of overtime. When I had the stomach operation I was "bored out of my mind" and invented a screened enclosure that has now saved my employer an estimated SEK 60 million (about US$7 million).

While Maj-Lis was so sick I have been thinking about a high-quality sawtooth-generator with almost perfect linearity. See the above link, but skip the EPROM. I mean to use the binary directly to the R2R ladder. Bu I have an idea.

PROBLEM
If the output covers up to 1MHz, then the divider must work at up to 128MHz. Not practical for me. The R2R ladder is also restricted in frequency. But how to get the maximum possible?

If I increase the steps by x2 (8-bits) to get 256 steps, then the problem gets worse.

IDEA
I can live with up to 200kHz and 7-digit binary, but the top frequency is then 25MHz, JUST about do-able. Max 100kHz and 8-bit I can use, but I will give it a try. I am still likely to see 256 steps, so here is an idea.

The R2R ladder uses 10K resistors, with a 20K ohm feed with binary at each junction. So why not use TWO CD4040 counters? Both running in parallel. The clock to one counter is inverted, so it counts the same as the first counter, but 1/2 cycle behind.

Instead of using 20K resistors to feed each 10K junction, I use two 40K resistors, one from each counter?

In effect I will still get an R2R ladder, but with two counters, one delayed by 1/2 a cycle, so instead of 256 steps I get 1024 steps, with a binary division of only 256.

I will try to post a drqawing shortly, but Maj-Lis needs my attention now.

BR Harry - SM0VPO