PLL with discrete chips - Upgrade Joy design solving major issue - V2.0

Gigillo, 

Thanks for posting your circuit, I have been interested in synthesizers on and off ever since the CMOS synthesizer project appeared on HHH all those years ago. Since I learned the basics of PIC programming I am now more interested in serial loaded PLL chips and have used the MC145145 and the MC145157. I have found these to be available from China for very low prices. They were so cheap that I expected them to be fake but they do seem to work well. I would imagine these devices are obselete now and being sold off as surplus stock. Incidentally if you need an MC145152 parallel load type ex-PMR VHF radios are a good source. These units are cheap now that chinese VHF radios (Baofeng, etc.) are so cheap that PMR conversion is no longer worthwhile. 

I too have struggled with loop filter design and was put off by the maths. Last week I wrote an excel spreadsheet to calculate component values and despite my calculations agreeing with others [http://www.g4jnt.com/VHF_Synth_Module.pdf] in practice the calculated values did not stabilise the loop. In the end I used trial and error by trying out different R/C values and looking at the Lock Detect signal on the oscilloscope, tweaking for the narrowest pulses to 0v. I have not had any success with the phiR/phiV and op amp arrangement but have had good loop stability using simple RC filters on the PDout pin. 

One idea I had a few years ago was to vary the reference frequency as well as the N counter to get fine tuning steps but with a high reference frequency. With the MC145145 the R counter can be any value from 3 to 4095, but I dont know if the loop filtering would be more difficult if the reference is a variable rather than fixed value. 

I am also looking into 2-loop synthesizer designs having seen this: 
http://ei4dib.blogspot.com/2015/09/pe1jpd-projects-and-kits70-mhz-all-mode.html
I was confused at first, but if you have 2 PLLs with 10 and 11kHz reference frequencies you can move in 1kHz steps by increasing the N counter of 1 PLL whilst decreasing the N counter of the other, for example (300*10 +200*11) =5200. (299*10 + 201*11) = 5201. At least, that's my understanding. I believe this idea can be extended to get, say, 100Hz steps for SSB, etc. 

Regards,
John

Hello everyone, thank you for accepting me in this wonderful forum.
I am an Italian HAM who really likes the self-construction of his radio equipment and who likes to experiment in the field of radiofrequency.
In the recent past, I met Joy through the web, a fan like me of RF. Together with him, I design PCB and realize the circuit that he designed and that you can find at this link: https://sm0vpo.forumotion.com/t604-144-148mhz-pll-with-discrete-chips .
The circuit had several issues and once fixed, it works perfectly.
Now a 2.0 version was needed that was able to extend the ease of use of the board and would allow it to be used with all frequencies below 200mhz.
So the 2.0 version was born, of which I report, below, the schematic diagram.
There is still a small issue to solve and to tune, the LPF of the PLL.
it consist in a tone that is heard together with the RF carrier.
Since the v1.0 board was being debugged, I would like to wait for the assembly of the 2.0 version of which I am waiting for the PCB.
Once assembled I will post its photo and possibly the problem if it occurs again.
If you have any suggestions, I'm here to listen to them.
Thanks for the attention.